Integrated circuit (IC) chips, such as an ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. A ULSI circuit may include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorous).
The source and drain regions often include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects (SCE), which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier lowering. Controlling short-channel effects is particularly important as transistors and gate lengths become smaller.
As transistors disposed on integrated circuit chips become smaller (e.g., transistors with gate lengths less than 100 nm), CMOS fabrication processes have utilized a two-dimensional channel-doping technique. FIG. 1 shows an illustrative conventional transistor 20 provided on a portion 22 of an integrated circuit. The transistor 20 is provided between isolation regions 24, and it includes source and drain regions 26 and a gate structure 28. The gate structure 28 includes a gate dielectric 30, and a gate electrode 32. A spacer structure 34 is formed along sidewalls of the gate structure 28.
The gate dielectric 30 is located between and partially over a source extension 36 and a drain extension 38 (e.g., above a channel region 40). A silicide layer 42 is formed over gate electrode 32 and over the source and drain regions 26. The transistor 20 includes shallow pocket regions 44, which help suppress the short-channel effect. Short-channel effects are undesirable and degrade the robustness of the transistor 20 to random process variations. The shallow pocket regions 44 are provided in a conventional CMOS pocket implant process. This implant process is performed after gate structure 28 is fabricated and before silicide layer 42 is formed. The size and placement of the pocket regions 44 may vary from that shown in FIG. 1. For example, FIG. 2 shows another illustrative transistor device 20 having larger and deeper, yet localized pocket regions 46, which are currently more preferred in the semiconductor industry by many manufacturers. Generally, it is desired that the pocket regions 46 are deep enough to suppress punch through effects. However, a “halo-like structure” 48, as shown in FIG. 3 for example, is currently less desired than localized pocket regions 46 (see FIG. 2) because the halo regions 48 extend below the source and drain regions 26. The halo-like structure of pocket regions 48 in FIG. 3 tend to increase the doping concentration near the junction of source and drain regions 26. Increased doping concentration near the junction of source and drain regions 26 degrades (i.e., increases) the source/drain junction capacitance (e.g., parasitic capacitance) and, hence, reduces the speed of transistor 20.
A need exists for manufacturing methods allowing for better dopant grading in the source and drain regions without causing increases in adverse short-channel effects and junction capacitance.